Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are hardware description language (HDL) creation for a system and synthesis, placement, and routing of the system on the target device.
Partial reconfiguration (PR) involves designing a plurality of instances for a PR module on a programmable target device during compilation. Each instance of a PR module represents a different circuit description that can be implemented for the PR module. A selected PR module may be reconfigured from a first instance to a second instance while other PR modules and static modules on the programmable target device remain in active operation.
PR allows a portion of a system to be reconfigured with a programming file created by an EDA tool that represents only that portion of the target device, unlike a typical programming file representing an entire programmable target device. PR also allows a system to be reconfigured without having to power down the programmable target device for the reprogramming. PR can be used for feature upgrades or changes, bug fixes, or any other operation on a device that requires reprogramming without requiring down time to be taken for unaffected portions of the device.